
module testbench(); 
    reg clk, rst_n, D_in; 
wire match, not_match; 
reg [23:0] data; 
    initial begin 
        clk=0; 
        rst_n=0; 
        D_in=0; 
        data=24'b011100_011010_011110_011101; 
        #20; 
        rst_n=1; 
    end 
always #10 clk<=~clk; 
always@(posedge clk)begin 
    D_in <= data[23]; 
    data <= {data[22:0],data[23]}; 
end 
    sequence_detect test( 
        .clk(clk), 
        .rst_n(rst_n), 
        .data(D_in), 
        .match(match), 
        .not_match(not_match) 
    ); 
endmodule 